eProcessor is in ISC 2024
eProcessor is presented in the Euro-HPC booth’s video! Moreover, do come to see our presentation and talk with our team on Tuesday from 11:00 to 11:30 at EuroHPC booth !
eProcessor is presented in the Euro-HPC booth’s video! Moreover, do come to see our presentation and talk with our team on Tuesday from 11:00 to 11:30 at EuroHPC booth !
We are glad to be in HiPEAC 2024 in Munich !!. On Wednesday at 12:30 you can see our presentation of where eProcessor stands, at EuroHPC Projects Shaping Europe’s HPC Landscape Workshop and on Thursday and Friday our poster and our exploitation manager will be on the 1st floor looking forward to your discussions !
In order to meet the increased computational demands and stricter power constraints of modern applications, architectures have evolved to include domain-specific dedicated accelerators. In order to design efficient accelerators, three main components need to be addressed: compute, memory, and control. Moreover, since SoCs usually contain multiple accelerators, selecting the right one for each task also become crucial. This becomes specially […]
science with practical applications ranging from pattern matching to computational biology. The ever-increasing volumes of genomic data produced by modern DNA sequencers motivate improved software and hardware sequence alignment accelerators that scale with longer sequence lengths and high error rates without losing accuracy. Furthermore, the wide variety of use cases requiring sequence alignment demands flexible and efficient solutions that can […]
Energy-efficient execution of task-based parallel applications is crucial as tasking is a widely supported feature in many parallelprogramming libraries and runtimes. Currently, state-of-the-art proposals primarily rely on leveraging core asymmetry and CPUDVFS. Additionally, these proposals mostly use heuristics and lack the ability to explore the trade-offs between energy usage andperformance. However, our findings demonstrate that focusing solely on CPU energy […]
The eProcessor project aims at creating a RISC-V full stack ecosystem. The eProcessor architecture combines a high-performance out-of-order core with energy-efficient accelerators for vector processing and artificial intelligence with reduced-precision functional units. The design of this architecture follows a hardware/software co-design approach with relevant application use cases from the high-performance computing, bioinformatics and artificial intelligence domains. Two eProcessor prototypes will […]
We are joining RISC-V summit Europe tomorrow! Ours John Davis will discuss Collaboration and Culture: Leveraging Diverse Strengths to Cultivate a Stronger Community (@ 8.00 AM) as well as EU & RISK-V (@ 17:15). Do come and join us!
The eProcessor vector accelerator design supports the IEEE754 double (64-bit) and single (32-bit) precision formats (FP64/32), the 16-bit “brain floating-point” format (BF16), and two different 8-bit format, 1-4-3 and 1-5-2, referred to as “Hybrid 8-bit Floating Point” (HFP8). While the wider formats are appropriate for the traditional scientific applications, small precision floating point formats are gaining interest for AI computing […]
eProcessor is presented in both the Poster Sessions and the Euro-HPC booth. Do come to see our demo and discuss how eProcessor can be of use for you !
eProcessor and our communications partner EXAPSYS are part of the largest ever MIT Global Startup Workshop (MIT GSW) with well over 1000 particpants. Come and visit us in our booth