eProcessor Simulator in a nutshell
July 22, 2025
eProcessor
European, extendable, energy-efficient, extreme-scale, extensible, Processor Ecosystem
Our motivation
The eProcessor project aims to build a new open OoO processor and accelerators and deliver a completely open European full-stack ecosystem
eProcessor technology will be extendable, energy efficient, extreme-scale, suitable for uses in HPC and embedded applications, and extensible.
Our Unique Value Proposition
eProcessor offers an open complete hardware-software stack for HPC systems utilizing cutting-edge mainly open-source technologies based on the RISC-V architecture providing a hardware device (eProcessor TC1 chip), a HW emulation system (the multi-core FPGA SDV), an advanced simulation system (on top of GEM5) and the corresponding low-level SW which all allow for the efficient development of advanced HPC applications and systems.
Our approach
- Software/hardware co-design for improved application performance and energy efficiency
- HPC
- HPDA (AI/ML/DL)
- Bioinformatics
- High performance Out-of-Order (OOO) 64-bit RISC-V platform
- 4-way OOO Core
- Single core & multi-core designs
- Multi-socket, cache coherent implementation
- Adaptive caches, HW/SW fault tolerance
- On chip Vector + AI + Bioinformatics accelerator co-processor, reduced & mixed-precision
- Cache-coherent off-chip CNN accelerator
eProcessor video
News & Events
eProcessor’s application in a nutshell
March 4, 2025
Task Scheduling in a nutshell
September 12, 2024
eProcessor is in ISC 2024
May 1, 2024
Chip-to-Chip (C2C) in a nutshell
February 23, 2024
eProcessor is in HiPEAC 2024
January 16, 2024
eProcessor is part of RISC-V summit Europe 2023
June 6, 2023
Our news in LinkedIn
The partners
