Barcelona Supercomputing Center (BSC)

The Barcelona Supercomputing Center (BSC) was established in 2005 and is the Spanish national supercomputing facility and a hosting member of the PRACE distributed supercomputing infrastructure. The Center houses MareNostrum, one of the most powerful supercomputers in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress.

BSC was a pioneer in combining HPC service provision, and R&D into both computer and computational science (life, earth and engineering sciences) under one roof. The centre fosters multidisciplinary scientific collaboration and innovation and currently has over 600 staff members from 47 countries. In 2011, BSC was one of only eight Spanish research centres recognized by the national government as a “Severo Ochoa Centre of Excellence”, and it was again awarded with this prestigious recognition in 2015.

BSC has collaborated with industry since its creation, and has participated in projects with companies such as ARM, Bull and Airbus as well as numerous SMEs. BSC also participates in various bilateral joint research centers with companies such as IBM, Microsoft, Intel, NVIDIA and Spanish oil company Repsol. The centre has been extremely active in the EC Framework Programmes and has participated in over one hundred projects funded by it. BSC is a founding member of HiPEAC, the ETP4HPC and participates in the most relevant international roadmapping and discussion forums and has strong links to Latin America.

Education and Training is a priority for the centre and many of BSCs researchers are also university lecturers. BSC offers courses as a PRACE Advanced Training Centre, and through the Spanish national supercomputing network among others.

The BSC-CNS Computer Sciences Department focuses on building upon currently available hardware and software technologies and adapting these technologies to make efficient use of supercomputing infrastructures. The department proposes novel architectures for processors and memory hierarchy and develops programming models and innovative implementation approaches for these models as well as tools for performance analysis and prediction.

Main tasks attributed in the project

BSC coordinates the ePROCESSOR project and contributes to several WPs in providing its knowledge of hardware design, FPGA emulation, benchmarking, and system simulation tools. BSC leads WP3 where the evaluation of the different design parts and benchmarking is carried out, and WP5 where the target ePROCESSOR design is developed.

BSC will contribute to the design of an energy-efficient high performing RISC-V core, which will be emulated on an FPGA together with the other IPs of the project. This RISC-V core will also be fabricated during the life of the project. BSC will leverage the experience designing the RISC-V vector accelerator for HPC workloads for the case studies of this project, exploring different implementations optimized for energy efficiency using short vector lengths, as well as vector core fusion techniques. Finally, BSC will provide open source benchmarks interesting for different application domains such as automotive, deep learning and HPC.