The RISC-V IOMMU of eProcessor in a Nutshell

In today’s high performance computer systems and particularly the more resource-intensive ones, like servers, the I/O transactions that read data from a hard disk or a network card, constitute a significant part of the overall workload, making them an essential part for a successful system in terms of performance. Most of today’s peripheral devices bypass the processor to minimize the […]

Read More

eProcessor cache coherence in a Nutshell

Multi-core processors have become ubiquitous across domains ranging from embedded systems to data centers because of their ability to facilitate energy-efficient high performance computing. The architecture of a typical multi-core processor mainly comprises cores that are the computational workhorses, caches that act as buffers to reduce access latency to memory and an interconnection network that connects all the on chip […]

Read More

eProcessor in a Nutshell : The Future is Here !

The eProcessor project is an ambitious combination of processor design, based on the RISC-V open source hardware ISA, applications and system software, bringing together multiple partners to leverage and extend pre-existing Intellectual Property (IP), combined with new IP that can be used as building blocks for future HPC systems, both for traditional and emerging application domains. As such, the eProcessor […]

Read More