eProcessor Presented in HPCA’s workshop

We are happy that our paper entitled “Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs” by Miquel Moreto and Santiago Marco-Sola was presented at 4th HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (https://aacbb-workshop.github.io/).

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“FastTrackNoC: A NoC with FastTrack Router Datapaths” published in 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

This paper introduces FastTrackNoC, a Network-on-Chip (NoC) router architecture that reduces packet latency by bypassing its switch traversal (ST) stage. It is based on the observation that there is a bias in the direction a flit takes through a router, e.g., in a 2D mesh network, non-turning hops are preferred, especially when dimension order routing is used. FastTrackNoC capitalizes on […]

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“FPGA Checkpointing for Scientific Computing” – Marc Perelló Bacardit, Leonardo Bautista-Gomez, Osman Unsal; at the 27th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’21)

Abstract—The use of FPGAs in computational workloads is becoming increasingly popular due to the flexibility of these devices in comparison to ASICs, and their low power consumption compared to GPUs and CPUs. However, scientific applications run for long periods of time and the hardware is always subject to failures due to either soft or hard errors. Thus, it is important […]

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