Publications

Mika, K., Porrmann, F., Kucza, N., Griessl, R., & Hagemeyer, J. “RECS: A Scalable Platform for Heterogeneous Computing”. 2023 IEEE 36th International System-on-Chip Conference (SOCC),https://doi.org/10.1109/SOCC58585.2023.10256982

Jing Chen, Madhavan Manivannan, Bhavishya Goel and Miquel Pericàs, “SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs,” 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, CA, USA, 2024, pp. 325-336, doi: 10.1109/IPDPS57955.2024.00036.

M. Vázquez, M. W. Azhar and P. Trancoso, “Exploiting the Potential of Flexible Processing Units,” 2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Porto Alegre, Brazil, 2023, pp. 34-45, doi: 10.1109/SBAC-PAD59825.2023.00013.

Max Doblas Font, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova, Christopher Batten, Santiago Marco-Sola, and Miquel Moreto. “GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment.” 56th ACM/IEEE Int’l Symp. on Microarchitecture (MICRO), Oct. 2023.

Jing Chen, Madhavan Manivannan, Bhavishya Goel, and Miquel Pericàs. “JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency”. In Proceedings of the 52nd International Conference on Parallel Processing (ICPP ’23). Association for Computing Machinery, New York, NY, USA, 828–838. https://doi.org/10.1145/3605573.3605586

Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto Gonzalez, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vasilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, and Ioannis Papaefstathiou. “EProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem”. In Proceedings of the 20th ACM International Conference on Computing Frontiers (CF ’23). Association for Computing Machinery, New York, NY, USA, 309–314. https://doi.org/10.1145/3587135.3592178

M. V. Maceiras, M. Waqar Azhar and P. Trancoso, “VSA: A Hybrid Vector-Systolic Architecture,” 2022 IEEE 40th International Conference on Computer Design (ICCD), Olympic Valley, CA, USA, 2022, pp. 368-376, doi: 10.1109/ICCD56317.2022.00061

Josue Quiroga, Roberto Ignacio Genovese, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez, “Reusable Verification Environment for a RISC-V Vector Accelerator”, DVcon 2022

Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas.”STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures”, In Proceedings IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022).

Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, and Miquel Pericàs, “ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes.” In ACM Transaction of Architecture and Code Optimization (TACO) 19, 2, Article 27

This project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 956702. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Spain, Sweden, Greece, Italy, France, Germany.

Legal Notice

Financed by the European Union – NextGeneration EU

Web design by Edgy Digital Agency

Publications

© 2025 - All rights reserved