| D1.1 | Project Management and Quality Guidelines |
| D1.2 | Data Management Plan (DMP) |
| D2.1 | Dissemination and communication plan and Exploitation strategy |
| D2.2 | Dissemination and communication report |
| D2.3 | Exploitation progress report |
| D2.4 | Final dissemination and communication report |
| D2.5 | Final exploitation plan |
| D3.1 | Use cases definition, requirements and specifications reports |
| D3.2 | Microbenchmarks suite to drive design optimizations |
| D3.3 | Initial porting of the use case |
| D3.4 | Performance analysis and optimizations of the use case |
| D3.5 | Set of optimized applications and final evaluation |
| D4.1 | Release of the O/S, boot environment, compiler and performance tools for the FPGA-based single core system |
| D4.2 | Release of the O/S, boot environment, compiler and performance tools for the single-core fabricated design |
| D4.3 | Linux, application-level checkpointing, efficient resource management, optimized runtime systems and compilers, performance tools for the FPGA-based multi-core system |
| D4.4 | Linux, application-level checkpointing, efficient resource management, optimized runtime systems and compilers, performance tools on the final multi-core fabricated design |
| D5.1 | RTL and verification code for accelerators and functional units |
| D5.2 | RTL and verification code for OOO core |
| D5.3 | Integrated RTL source code for OOO core with accelerator units and verification IP (methodology and testbenches) |
| D5.4 | Integrated RTL source code for multicore, coherence and interconnect design and verification IP |
| D5.5 | Release of eProcessor RTL and verification source code |
| D6.1 | FPGA emulation infrastructure and development environment |
| D6.2 | Simulation infrastructure and early architectural explorations |
| D6.3 | FPGA emulation of single-core system |
| D6.4 | FPGA emulation of multi-core system and accelerators |
| D6.5 | Advanced architectural explorations and scaling studies |
| D7.3 | Final report on chip architecture, synthesis and physical design |
| D7.4 | Final report on PCB architecture, testing results, firmware and BSP |
