“FastTrackNoC: A NoC with FastTrack Router Datapaths” published in 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

This paper introduces FastTrackNoC, a Network-on-Chip (NoC) router architecture that reduces packet latency by bypassing its switch traversal (ST) stage. It is based on the observation that there is a bias in the direction a flit takes through a router, e.g., in a 2D mesh network, non-turning hops are preferred, especially when dimension order routing is used. FastTrackNoC capitalizes on […]

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eProcessor cache coherence in a Nutshell

Multi-core processors have become ubiquitous across domains ranging from embedded systems to data centers because of their ability to facilitate energy-efficient high performance computing. The architecture of a typical multi-core processor mainly comprises cores that are the computational workhorses, caches that act as buffers to reduce access latency to memory and an interconnection network that connects all the on chip […]

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eProcessor in a Nutshell : The Future is Here !

The eProcessor project is an ambitious combination of processor design, based on the RISC-V open source hardware ISA, applications and system software, bringing together multiple partners to leverage and extend pre-existing Intellectual Property (IP), combined with new IP that can be used as building blocks for future HPC systems, both for traditional and emerging application domains. As such, the eProcessor […]

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€8m project for Europe’s first RISC-V supercomputer chip

A European project is developing a high performance RISC-V processor for supercomputer designs and derivatives for automotive and edge IoT. The €8m eProcessor project is using a high-performance Out-of-Order (OoO) processor core based on the RISC-V instruction set architecture as the first high performance computing ecosystem. The three year project is led by the Barcelona Supercomputing Centre and is supported by […]

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This is eProcessor, a step forward to compete in hardware

With a budget of 8 million euros over the next three years, the eProcessor project aims to develop the first European open source chip. A chip with RISC-V architecture, which seeks to become the free alternative to Intel, AMD and ARM-based designs. The eProcessor project will be framed within other supercomputing projectssuch as the ‘European Processor Initiative’, ‘Low-Energy Toolset for Heterogeneous Computing’, […]

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eProcessor: A Major Component of European HPC

A major milestone towards building  entirely made-in-Europe future High Performance Computing (HPC) systems: 10 Partners from 6 EU Member States join forces to build the first 100% European out-of-order (OoO) RISC-V core, a set of advanced tightly couple accelerators, as well as the novel software suite which will take full advantage of the novel processing unit. The eProcessor ecosystem combines […]

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“FPGA Checkpointing for Scientific Computing” – Marc Perelló Bacardit, Leonardo Bautista-Gomez, Osman Unsal; at the 27th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’21)

Abstract—The use of FPGAs in computational workloads is becoming increasingly popular due to the flexibility of these devices in comparison to ASICs, and their low power consumption compared to GPUs and CPUs. However, scientific applications run for long periods of time and the hardware is always subject to failures due to either soft or hard errors. Thus, it is important […]

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