Small precision Floating Point support in eProcessor in a nutshell

The eProcessor vector accelerator design supports the IEEE754 double (64-bit) and single (32-bit) precision formats (FP64/32), the 16-bit “brain floating-point” format (BF16), and two different 8-bit format, 1-4-3 and 1-5-2, referred to as “Hybrid 8-bit Floating Point” (HFP8). While the wider formats are appropriate for the traditional scientific applications, small precision floating point formats are gaining interest for AI computing […]

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“STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures”, by Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas to be presented in IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022).

Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a cluster. Recent approaches that focus on energy efficient […]

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“ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes.” by Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, and Miquel Pericàs, published in ACM Transaction of Architecture and Code Optimization (TACO) 19, 2, Article 27

Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein […]

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eProcessor Presented in HPCA’s workshop

We are happy that our paper entitled “Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs” by Miquel Moreto and Santiago Marco-Sola was presented at 4th HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (https://aacbb-workshop.github.io/).

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