We are happy that our paper entitled “Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs” by Miquel Moreto and Santiago Marco-Sola was presented at 4th HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (https://aacbb-workshop.github.io/).
Our brand new poster attracted much attention at HiPEAC 2022! FORTH has also presented eProcessor as part of the very succesful DL4IoT’s workshop on Deep Learning for IoT !
Thanks to the Cognitronics and Sensor Systems group of Bielefeld University eProcessor has been presented in Hannover Messe 2022. Interesting talks and vast interest for our, soon to be, eProcessor-based smart mirror.
This paper introduces FastTrackNoC, a Network-on-Chip (NoC) router architecture that reduces packet latency by bypassing its switch traversal (ST) stage. It is based on the observation that there is a bias in the direction a flit takes through a router, e.g., in a 2D mesh network, non-turning hops are preferred, especially when dimension order routing is used. FastTrackNoC capitalizes on […]
eProcessor has been presented at the ‘Parallel Programming’ course at Koç University as part of the eProcessor-Sparcity EuroHPC collaboration plan on Monday 8/11/2021 !
Multi-core processors have become ubiquitous across domains ranging from embedded systems to data centers because of their ability to facilitate energy-efficient high performance computing. The architecture of a typical multi-core processor mainly comprises cores that are the computational workhorses, caches that act as buffers to reduce access latency to memory and an interconnection network that connects all the on chip […]
The eProcessor project is an ambitious combination of processor design, based on the RISC-V open source hardware ISA, applications and system software, bringing together multiple partners to leverage and extend pre-existing Intellectual Property (IP), combined with new IP that can be used as building blocks for future HPC systems, both for traditional and emerging application domains. As such, the eProcessor […]
A European project is developing a high performance RISC-V processor for supercomputer designs and derivatives for automotive and edge IoT. The €8m eProcessor project is using a high-performance Out-of-Order (OoO) processor core based on the RISC-V instruction set architecture as the first high performance computing ecosystem. The three year project is led by the Barcelona Supercomputing Centre and is supported by […]
With a budget of 8 million euros over the next three years, the eProcessor project aims to develop the first European open source chip. A chip with RISC-V architecture, which seeks to become the free alternative to Intel, AMD and ARM-based designs. The eProcessor project will be framed within other supercomputing projectssuch as the ‘European Processor Initiative’, ‘Low-Energy Toolset for Heterogeneous Computing’, […]
Watch our talk on eProcessor’s RISC-V at 2nd workshop on RISC-V and OpenPOWER in HPC at the ICS International Conference on Supercomputing 2021 : More info here.