Sapienza is the largest university in Europe with over 112000 students and 4000 faculty employees, organized in 59 Departments. The Department of Information Engineering, Electronics and Telecommunications (DIET) of Sapienza University will contribute eProcessor with the design of custom-precision units and their integration in the vector accelerator of the processor core. The focus will be on dynamically supporting multiple 8-bit floating point formats, targeting embedded HPC very-low-power applications. The activity will produce an RTL IP ready to be integrated in the vector lanes, leveraging previous experience in the European Processor Initiative accelerator design, in which UNIRM participates as a third party of BSC. UNIRM also contributes to the requirement definition as well the dissemination activities, as it is in the mission of its academic/research type of institution.
UNIRM’s personnel that will contribute to eProcessor has a general, consolidated experience in digital and mixed-signal integrated circuit design as well as FPGA prototyping of digital architectures. Specifically related to the eProcessor topics, UNIRM has experience in designing RISC-V processor cores and accelerators, targeting the HPC, embedded and fault-tolerant applications, e.g. the EPI project as well as the design of the Klessydra processor core family.