The eProcessor proposal goes beyond the traditional HPC usage domain, expands to High Performance Data Analytics (HPDA), Deep Learning and AI workloads, and mixed-precision processing technologies for genomic processing in the Bioinformatics domain.
- Explore new areas in reduced precision, sparsity, and software/hardware co-design.
- Allow the OpenMP runtime and compiler to guide cache coherence optimizations and to implement energy-efficient scheduling and synchronization; as well as to integrate Tensorflow.
- Advance the state-of-the-art for the ML accelerators by developing arithmetic units to support simultaneously a wide range of reduced and mixed precision (1, 2, 4, 8-bit) as well as explore new formats (8- and 16-bit bfloat) for reduced precision floating-point for ML training.
- Improve application performance using cooperative adaptive on-chip memories (scratchpad for last-level cache).
- Devise a Coherent CPU/Accelerator NoC Interconnect.
- Provide Fault Tolerance for critical processor structures such as L1 Data & Instruction caches, L2 cache, TLB, and register files with various error detection strengths (parity or lightweight ECC).
