“FastTrackNoC: A NoC with FastTrack Router Datapaths” published in 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
This paper introduces FastTrackNoC, a Network-on-Chip (NoC) router architecture that reduces packet latency by bypassing its switch traversal (ST) stage. It is based on the observation that there is a bias in the direction a flit takes through a router, e.g., in a 2D mesh network, non-turning hops are preferred, especially when dimension order routing is used. FastTrackNoC capitalizes on […]