In order to meet the increased computational demands and stricter power constraints of modern applications, architectures have evolved to include domain-specific dedicated accelerators. In order to design efficient accelerators, three main components need to be addressed: compute, memory, and control. Moreover, since SoCs usually contain multiple accelerators, selecting the right one for each task also become crucial. This becomes specially […]
science with practical applications ranging from pattern matching to computational biology. The ever-increasing volumes of genomic data produced by modern DNA sequencers motivate improved software and hardware sequence alignment accelerators that scale with longer sequence lengths and high error rates without losing accuracy. Furthermore, the wide variety of use cases requiring sequence alignment demands flexible and efficient solutions that can […]
We are joining RISC-V summit Europe tomorrow! Ours John Davis will discuss Collaboration and Culture: Leveraging Diverse Strengths to Cultivate a Stronger Community (@ 8.00 AM) as well as EU & RISK-V (@ 17:15). Do come and join us!
The eProcessor vector accelerator design supports the IEEE754 double (64-bit) and single (32-bit) precision formats (FP64/32), the 16-bit “brain floating-point” format (BF16), and two different 8-bit format, 1-4-3 and 1-5-2, referred to as “Hybrid 8-bit Floating Point” (HFP8). While the wider formats are appropriate for the traditional scientific applications, small precision floating point formats are gaining interest for AI computing […]
eProcessor is presented in both the Poster Sessions and the Euro-HPC booth. Do come to see our demo and discuss how eProcessor can be of use for you !
eProcessor and our communications partner EXAPSYS are part of the largest ever MIT Global Startup Workshop (MIT GSW) with well over 1000 particpants. Come and visit us in our booth
Come and see a demo of eProcessor at Embedded World 2023 in Nuremerg from March 14-16, 2023.on the VEDLIoT booth in Hall 3-150.
Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a cluster. Recent approaches that focus on energy efficient […]
Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein […]
We are happy that our paper entitled “Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs” by Miquel Moreto and Santiago Marco-Sola was presented at 4th HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (https://aacbb-workshop.github.io/).