eProcessor is in HiPEAC 2024

We are glad to be in HiPEAC 2024 in Munich !!. On Wednesday at 12:30 you can see our presentation of where eProcessor stands, at EuroHPC Projects Shaping Europe’s HPC Landscape Workshop and on Thursday and Friday our poster and our exploitation manager will be on the 1st floor looking forward to your discussions !

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Vázquez, Mateo & Azhar, Muhammad & Trancoso, Pedro. Exploiting the Potential of Flexible Processing Units. 34-45. 10.1109/SBAC-PAD59825.2023.00013.

In order to meet the increased computational demands and stricter power constraints of modern applications, architectures have evolved to include domain-specific dedicated accelerators. In order to design efficient accelerators, three main components need to be addressed: compute, memory, and control. Moreover, since SoCs usually contain multiple accelerators, selecting the right one for each task also become crucial. This becomes specially […]

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Max Doblas Font, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova, Christopher Batten, Santiago Marco-Sola, and Miquel Moreto. “GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment.” 56th ACM/IEEE Int’l Symp. on Microarchitecture (MICRO), Oct. 2023.

science with practical applications ranging from pattern matching to computational biology. The ever-increasing volumes of genomic data produced by modern DNA sequencers motivate improved software and hardware sequence alignment accelerators that scale with longer sequence lengths and high error rates without losing accuracy. Furthermore, the wide variety of use cases requiring sequence alignment demands flexible and efficient solutions that can […]

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Small precision Floating Point support in eProcessor in a nutshell

The eProcessor vector accelerator design supports the IEEE754 double (64-bit) and single (32-bit) precision formats (FP64/32), the 16-bit “brain floating-point” format (BF16), and two different 8-bit format, 1-4-3 and 1-5-2, referred to as “Hybrid 8-bit Floating Point” (HFP8). While the wider formats are appropriate for the traditional scientific applications, small precision floating point formats are gaining interest for AI computing […]

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“STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures”, by Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas to be presented in IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022).

Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a cluster. Recent approaches that focus on energy efficient […]

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“ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes.” by Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, and Miquel Pericàs, published in ACM Transaction of Architecture and Code Optimization (TACO) 19, 2, Article 27

Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein […]

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