eProcessor is in HiPEAC 2024

We are glad to be in HiPEAC 2024 in Munich !!. On Wednesday at 12:30 you can see our presentation of where eProcessor stands, at EuroHPC Projects Shaping Europe’s HPC Landscape Workshop and on Thursday and Friday our poster and our exploitation manager will be on the 1st floor looking forward to your discussions !

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M. Vázquez, M. W. Azhar and P. Trancoso, “Exploiting the Potential of Flexible Processing Units,” 2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Porto Alegre, Brazil, 2023, pp. 34-45, doi: 10.1109/SBAC-PAD59825.2023.00013.

In order to meet the increased computational demands and stricter power constraints of modern applications, architectures have evolved to include domain-specific dedicated accelerators. In order to design efficient accelerators, three main components need to be addressed: compute, memory, and control. Moreover, since SoCs usually contain multiple accelerators, selecting the right one for each task also become crucial. This becomes specially […]

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Max Doblas Font, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova, Christopher Batten, Santiago Marco-Sola, and Miquel Moreto. “GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment.” 56th ACM/IEEE Int’l Symp. on Microarchitecture (MICRO), Oct. 2023.

science with practical applications ranging from pattern matching to computational biology. The ever-increasing volumes of genomic data produced by modern DNA sequencers motivate improved software and hardware sequence alignment accelerators that scale with longer sequence lengths and high error rates without losing accuracy. Furthermore, the wide variety of use cases requiring sequence alignment demands flexible and efficient solutions that can […]

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Jing Chen, Madhavan Manivannan, Bhavishya Goel, and Miquel Pericàs. “JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency”. In Proceedings of the 52nd International Conference on Parallel Processing (ICPP ’23). Association for Computing Machinery, New York, NY, USA, 828–838. https://doi.org/10.1145/3605573.3605586

Energy-efficient execution of task-based parallel applications is crucial as tasking is a widely supported feature in many parallelprogramming libraries and runtimes. Currently, state-of-the-art proposals primarily rely on leveraging core asymmetry and CPUDVFS. Additionally, these proposals mostly use heuristics and lack the ability to explore the trade-offs between energy usage andperformance. However, our findings demonstrate that focusing solely on CPU energy […]

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Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto Gonzalez, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vasilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, and Ioannis Papaefstathiou. “EProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem”. In Proceedings of the 20th ACM International Conference on Computing Frontiers (CF ’23). Association for Computing Machinery, New York, NY, USA, 309–314. https://doi.org/10.1145/3587135.3592178

The eProcessor project aims at creating a RISC-V full stack ecosystem. The eProcessor architecture combines a high-performance out-of-order core with energy-efficient accelerators for vector processing and artificial intelligence with reduced-precision functional units. The design of this architecture follows a hardware/software co-design approach with relevant application use cases from the high-performance computing, bioinformatics and artificial intelligence domains. Two eProcessor prototypes will […]

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Small precision Floating Point support in eProcessor in a nutshell

The eProcessor vector accelerator design supports the IEEE754 double (64-bit) and single (32-bit) precision formats (FP64/32), the 16-bit “brain floating-point” format (BF16), and two different 8-bit format, 1-4-3 and 1-5-2, referred to as “Hybrid 8-bit Floating Point” (HFP8). While the wider formats are appropriate for the traditional scientific applications, small precision floating point formats are gaining interest for AI computing […]

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