eProcessor at Embedded World 2023
Come and see a demo of eProcessor at Embedded World 2023 in Nuremerg from March 14-16, 2023.on the VEDLIoT booth in Hall 3-150.
eProcessor is in HiPEAC 2023
We are glad to be in HiPEAC 2023 in Toulouse !!. We are presenting the project in the EU Projects’ poster day
M. V. Maceiras, M. Waqar Azhar and P. Trancoso, “VSA: A Hybrid Vector-Systolic Architecture,” 2022 IEEE 40th International Conference on Computer Design (ICCD), Olympic Valley, CA, USA, 2022, pp. 368-376, doi: 10.1109/ICCD56317.2022.00061
In order to deliver high performance efficiently, modern processors include dedicated hardware to accelerate different application domains. For example, several recent processors include dedicated Machine Learning (ML) accelerators. However, while adding dedicated hardware improves efficiency compared to general-purpose CPUs, it also requires a larger area, making it unfeasible for smaller devices. Therefore, exploring ways to use the existing hardware for […]
Josue Quiroga, Roberto Ignacio Genovese, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez, “Reusable Verification Environment for a RISC-V Vector Accelerator”, DVcon 2022
This paper presents a reusable verification environment developed for the verification of an academic RISC-V based vector accelerator that operates with long vectors. In order to be used across diverse projects, this infrastructure intends to be independent of the interface used for connecting the accelerator to the scalar processor core. We built a verification infrastructure consisting of a Universal Verification […]
Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas.”STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures”, In Proceedings IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022).
Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a cluster. Recent approaches that focus on energy efficient […]
Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, and Miquel Pericàs, “ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes.” In ACM Transaction of Architecture and Code Optimization (TACO) 19, 2, Article 27
Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein […]
eProcessor Presented in HPCA’s workshop
We are happy that our paper entitled “Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs” by Miquel Moreto and Santiago Marco-Sola was presented at 4th HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (https://aacbb-workshop.github.io/).
eProcessor at HiPEAC 2022
Our brand new poster attracted much attention at HiPEAC 2022! FORTH has also presented eProcessor as part of the very succesful DL4IoT’s workshop on Deep Learning for IoT !
eProcessor in Hannover Messe 2022
Thanks to the Cognitronics and Sensor Systems group of Bielefeld University eProcessor has been presented in Hannover Messe 2022. Interesting talks and vast interest for our, soon to be, eProcessor-based smart mirror.
A. Ejaz and I. Sourdis, “FastTrackNoC: A NoC with FastTrack Router Datapaths,” 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Korea, Republic of, 2022, pp. 971-985, doi: 10.1109/HPCA53966.2022.00075.
This paper introduces FastTrackNoC, a Network-on-Chip (NoC) router architecture that reduces packet latency by bypassing its switch traversal (ST) stage. It is based on the observation that there is a bias in the direction a flit takes through a router, e.g., in a 2D mesh network, non-turning hops are preferred, especially when dimension order routing is used. FastTrackNoC capitalizes on […]