eProcessor

Josue Quiroga, Roberto Ignacio Genovese, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez, “Reusable Verification Environment for a RISC-V Vector Accelerator”, DVcon 2022

December 10, 2022

Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas.”STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures”, In Proceedings IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022).

October 19, 2022

Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, and Miquel Pericàs, “ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes.” In ACM Transaction of Architecture and Code Optimization (TACO) 19, 2, Article 27

July 6, 2022

Μ. Moreto, S. Marco-Sola “Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs” 4th HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformaticse

July 2, 2022

eProcessor at HiPEAC 2022

June 28, 2022

eProcessor in Hannover Messe 2022

June 3, 2022

A. Ejaz and I. Sourdis, “FastTrackNoC: A NoC with FastTrack Router Datapaths,” 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Korea, Republic of, 2022, pp. 971-985, doi: 10.1109/HPCA53966.2022.00075.

May 18, 2022

The RISC-V IOMMU of eProcessor in a Nutshell

May 17, 2022

eProcessor organizes a workshop as part of HiPEAC Computing Systems Week (CSW 2022) 28/4/2022

April 15, 2022

eProcessor presented in Sparcity project

November 11, 2021