Posts – Page 2 – eProcessor

Jing Chen, Madhavan Manivannan, Bhavishya Goel, and Miquel Pericàs. “JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency”. In Proceedings of the 52nd International Conference on Parallel Processing (ICPP ’23). Association for Computing Machinery, New York, NY, USA, 828–838. https://doi.org/10.1145/3605573.3605586

September 15, 2023

Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto Gonzalez, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vasilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, and Ioannis Papaefstathiou. “EProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem”. In Proceedings of the 20th ACM International Conference on Computing Frontiers (CF ’23). Association for Computing Machinery, New York, NY, USA, 309–314. https://doi.org/10.1145/3587135.3592178

June 8, 2023

eProcessor is part of RISC-V summit Europe 2023

June 6, 2023

Small precision Floating Point support in eProcessor in a nutshell

May 30, 2023

eProcessor is part of ISC 2023

May 23, 2023

eProcessor in MIT Global Startup Workshop (MIT GSW)

March 30, 2023

eProcessor at Embedded World 2023

March 5, 2023

eProcessor is in HiPEAC 2023

January 4, 2023

M. V. Maceiras, M. Waqar Azhar and P. Trancoso, “VSA: A Hybrid Vector-Systolic Architecture,” 2022 IEEE 40th International Conference on Computer Design (ICCD), Olympic Valley, CA, USA, 2022, pp. 368-376, doi: 10.1109/ICCD56317.2022.00061

December 23, 2022

Josue Quiroga, Roberto Ignacio Genovese, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez, “Reusable Verification Environment for a RISC-V Vector Accelerator”, DVcon 2022

December 10, 2022

This project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 956702. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Spain, Sweden, Greece, Italy, France, Germany.

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Financed by the European Union – NextGeneration EU