This paper presents a reusable verification environment developed for the verification of an academic RISC-V based vector accelerator that operates with long vectors. In order to be used across diverse projects, this infrastructure intends to be independent of the interface used for connecting the accelerator to the scalar processor core. We built a verification infrastructure consisting of a Universal Verification […]

Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a cluster. Recent approaches that focus on energy efficient […]

Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein […]

We are happy that our paper entitled “Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs” by Miquel Moreto and Santiago Marco-Sola was presented at 4th HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (https://aacbb-workshop.github.io/).

This paper introduces FastTrackNoC, a Network-on-Chip (NoC) router architecture that reduces packet latency by bypassing its switch traversal (ST) stage. It is based on the observation that there is a bias in the direction a flit takes through a router, e.g., in a 2D mesh network, non-turning hops are preferred, especially when dimension order routing is used. FastTrackNoC capitalizes on […]